1. Field of the Invention
The present invention relates to a spike current reducing circuit which is generally formed of a semiconductor integrated circuit and is attached to an electric power amplifier, in which a coil is driven according to a switching method based on the pulse width modulation, to reduce a spike current occurring in a switching operation of the coil.
2. Description of Related Art
In a switching operation for driving a coil by using transistors, it is required to turn on and off an output transistor, though which an output current is sent to a load circuit, as fast as possible for the purpose of driving the coil at high efficiency and low ripple percentage.
However, various capacitive components exist in an output node of the output transistor connected to the load circuit. Therefore, when the output transistor is turned on, a large instantaneous current flows from a power source of the output transistor to the ground through the output transistor due to the capacitive components and a load inductance of the load circuit. This large instantaneous current is called a spike current.
Though this spike current flows in a short time, an amount of the spike current is large. Therefore, a spike noise of the power source occurs in a current line from the power source to the ground due to the spike current.
FIG. 6 is a characteristic view showing a time-current characteristic of a spike current occurring in a conventional spike current reducing circuit.
As shown in FIG. 6, a spike current causing a spike noise of the power source is estimated by using the time-current characteristic of the spike current. A first time period from the occurrence of a spike current to a peak time, at which the spike current reaches a peak value, depends on input/output characteristics of the output transistor. A second time period from the peak time to the end of the spike current depends on a capacitance-resistance (CR) discharge characteristic of the output transistor linearly changing with time. The time-current characteristic can be approximately expressed by a straight line in both the first and second time periods. Therefore, the time-current characteristic can be theoretically expressed by a triangle. In this triangle, a length of the base expresses a spike current occurrence time period xcex94T (the sum of the first and second time periods), and a height of the vertex expresses a spike current peak value Ip.
Here, a capacitive component of the CR discharge characteristic linearly changing with time is determined by a capacitance C of the output node of the output transistor, and the capacitance C is obtained as a sum of a load capacitance of the load circuit, an output capacitance of the output transistor and a backward recovery capacitance of a regenerative diode applied for the pulse width modulation control. The capacitance C is a fixed value. Therefore, an amount of a charge accumulated at the output node is also a fixed value.
To reduce the spike noise of the power source, it is required to lower the spike current peak value Ip. To lower the spike current peak value Ip, because of a relation Ixe2x88x9dQ/T (I: the spike current, Q: an amount of the charge of the output node, T: a charge pull-out time period), it is required to lengthen the time period required for pulling out the charge accumulated at the output node. For example, in a spike current peak value method of the conventional spike current reducing circuit, an output impedance of a driving circuit, from which a control signal is input to a control terminal (or a gate) of the output transistor, is heightened to lengthen a rise time period (or a turn-on time period) of the output transistor, and the charge accumulated at the output node is gradually pulled out when an on-resistance (a resistance in a turn-on state) of the output transistor is not sufficiently low. Therefore, the spike current peak value Ip is lowered.
In FIG. 6, an area of the triangle theoretically indicating the time-current characteristic of the spike current corresponds to an amount of the charge (Q=Ipxc3x97xcex94T/2) accumulated at the output node. In the above-described method, the theoretical spike current peak value Ip is, for example, lowered by half, to lower the theoretical spike current peak value Ip to a value Ip1, and the theoretical spike current occurrence time period xcex94T is lengthened to a time period xcex94T1. In this case, because the amount of the charge accumulated at the output node is constant, the spike current occurrence time period xcex94T1 is twice as long as the theoretical spike current occurrence time period xcex94T.
As is described above, in the conventional spike current reducing circuit, in cases where the spike current peak value Ip is lowered by a prescribed rate to lower the spike noise of the power source, the spike current occurrence time period xcex94T is lengthened by a rate inverse to the prescribed rate of the spike current peak value to maintain the charge amount Q=Ipxc3x97xcex94T/2.
In cases where the conventional spike current reducing circuit is applied for the pulse width modulation control, it is desired to heighten a carrier frequency for the pulse width modulation for the purpose of lowering the ripple percentage. However, because the spike current occurrence time period is lengthened in the conventional spike current reducing circuit, the heightening of the carrier frequency is suppressed. Also, because a masking operation and a filtering operation are performed during the spike current occurrence time period in a current chopper type pulse width modulation (PWM) control system, the precision in the detection of a very low current is degraded in the PWM control system in cases where the spike current occurrence time period is lengthened in the conventional spike current reducing circuit. Therefore, a problem has arisen that it is difficult in the conventional spike current reducing circuit to sufficiently lower both the spike current peak value and the spike current occurrence time period.
An object of the present invention is to provide, with due consideration to the drawbacks of the conventional spike current reducing circuit, a spike current reducing circuit in which both a spike current peak value and a spike current occurrence time period in a spike current are sufficiently lowered.
The object is achieved by the provision of a spike current reducing circuit comprising an output transistor having a control terminal for outputting a spike current according to a control signal received at the control terminal, and an output transistor driving circuit for sending the control signal to the control terminal of the output transistor through a signal line of a first low impedance in a first driving stage to drive the output transistor at a high speed, sending the control signal to the control terminal of the output transistor through a signal line of a high impedance in a second driving stage to drive the output transistor at a low speed, and sending the control signal to the control terminal of the output transistor through a signal line of a second low impedance in a third driving stage to drive the output transistor at a high speed.
In the above configuration, the impedance of the output transistor driving circuit for the control signal is changed stage by stage. Accordingly, both a spike current peak value and a spike current occurrence time period in the spike current can be sufficiently lowered in the spike current reducing circuit. Also, in cases where the spike current reducing circuit is applied for the pulse width modulation control, the pulse width modulation control can be quickly performed, and an adverse influence of the noise of the spike current can be reduced.
It is preferred that the output transistor driving circuit comprises a pull-up resistor, and a mirror transistor, which is connected with the output transistor in a mirror connection and is connected to the pull-up resistor through a signal line, for maintaining a voltage level of the signal line during the first driving stage and outputting a prescribed amount of sink current to change the voltage level of the signal line and to perform a transfer from the first driving stage to the second driving stage in response to the change of the voltage level of the signal line.
Therefore, a degree of the turn-on of the output transistor is rapidly detected by the output transistor driving circuit, and the change from the first driving stage to the second driving stage can be automatically performed at the optimum timing.
It is preferred that the change from the second driving stage to the third driving stage is performed in response to the change of an output voltage of the output transistor to a prescribed level.
Therefore, the change from the second driving stage to the third driving stage can be automatically performed at the optimum timing according to a remaining charge to be discharged through the output transistor.
It is preferred that the output transistor driving circuit comprises an inverter, having a threshold voltage adjusted according to the prescribed voltage level, for producing a trigger signal according to both the output voltage of the output transistor and the threshold voltage and changing the signal line of the high impedance in the second driving stage to the signal line of the second low impedance in the third driving stage according to the trigger signal.
Therefore, because the remaining charge is proportional to the output voltage of the output transistor, the change from the second driving stage to the third driving stage can be automatically performed at the optimum timing by adjusting the threshold voltage of the inverter.
It is preferred that a time-current characteristic of the spike current output from the output transistor is set almost in a trapezoid shape.
Therefore, both the spike current peak value and the spike current occurrence time period in the spike current can be sufficiently lowered.
It is preferred that the output transistor driving circuit comprises a first low impedance driving circuit through which the control signal is sent to the control terminal of the output transistor at the first low impedance in the first driving stage, a high impedance driving circuit through which the control signal is sent to the control terminal of the output transistor at the high impedance in the second driving stage, a second low impedance driving circuit through which the control signal is sent to the control terminal of the output transistor at the second low impedance in the third driving stage, and a changing circuit for changing the control signal flowing through the first low impedance driving circuit to the control signal flowing through the high impedance driving circuit by changing a voltage level applied to the first low impedance driving circuit in response to the outputting of a prescribed amount of sink current, and changing the control signal flowing through the high impedance driving circuit to the control signal flowing through the second low impedance driving circuit by changing an output voltage of the output transistor to a prescribed level.
Therefore, the change from the first driving stage to the second driving stage can be automatically performed by the changing circuit at the optimum timing, and the change from the second driving stage to the third driving stage can be automatically performed by the changing circuit at the optimum timing.
It is preferred that the second low impedance driving circuit comprises a plurality of second high impedance driving circuits arranged in parallel to each other, and the changing circuit comprises a plurality of inverters, which have a plurality of threshold voltage values different from each other and are connected to the second high impedance driving circuits respectively, for respectively making the control signal flow through the corresponding second high impedance driving circuit in cases where the output voltage of the output transistor is lowered to a value lower than the corresponding threshold value.
In the above configuration, the number of second high impedance driving circuits, through which the control signal is sent to the control terminal of the output transistor, is gradually increased in the third driving stage. Therefore, the change from the second driving stage to the third driving stage can be performed while smoothly changing the spike current value, and a time-current characteristic of the spike current can be set almost in an ideal trapezoid shape.